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19-1955; Rev 2; 1/03
KIT ATION EVALU BLE AVAILA
Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit MAX1845
General Description Features
o Ultra-High Efficiency o Accurate Current-Limit Option o Quick-PWMTM with 100ns Load-Step Response o 1% VOUT Accuracy over Line and Load o Dual ModeTM Fixed 1.8V/1.5V/Adj or 2.5V/Adj Outputs o Adjustable 1V to 5.5V Output Range o 2V to 28V Battery Input Range o 200/300/420/540kHz Nominal Switching Frequency o Adjustable Overvoltage Protection o 1.7ms Digital Soft-Start o Drives Large Synchronous-Rectifier FETs o Power-Good Window Comparator o 2V 1% Reference Output
The MAX1845 is a dual PWM controller configured for step-down (buck) topologies that provides high efficiency, excellent transient response, and high DC output accuracy necessary for stepping down high-voltage batteries to generate low-voltage chipset and RAM power supplies in notebook computers. The CS_ inputs can be used with low-side sense resistors to provide accurate current limits or can be connected to LX_, using low-side MOSFETs as current-sense elements. The on-demand PWM controllers are free running, constant on-time with input feed-forward. This configuration provides ultra-fast transient response, wide input-output differential range, low supply current, and tight load-regulation characteristics. The MAX1845 is simple and easy to compensate. Single-stage buck conversion allows the MAX1845 to directly step down high-voltage batteries for the highest possible efficiency. Alternatively, two-stage conversion (stepping down the 5V system supply instead of the battery at a higher switching frequency) allows the minimum possible physical size. The MAX1845 is intended for generating chipset, DRAM, CPU I/O, or other low-voltage supplies down to 1V. For a single-output version, refer to the MAX1844 data sheet. The MAX1845 is available in 28-pin QSOP and 36-pin thin QFN packages.
Ordering Information
PART MAX1845EEI MAX1845ETX TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 28 QSOP 36 Thin QFN 6mm 6mm
Applications
Notebook Computers CPU Core Supplies Chipset/RAM Supply as Low as 1V 1.8V and 2.5V I/O Supplies
5V INPUT
Minimal Operating Circuit
BATTERY 4.5V TO 28V VDD VCC ILIM1 ILIM2 ON1 ON2 BST1 OUTPUT1 1.8V DH1 LX1 DL1 V+ UVP OVP
MAX1845EEI
BST2 DH2 LX2 DL2 OUTPUT2 2.5V
CS2 TON CS1 OUT1 PGOOD OUT2 REF SKIP
Pin Configurations appear at end of data sheet. Quick-PWM and Dual Mode are trademarks of Maxim Integrated Products.
FB1 GND
FB2
________________________________________________________________ Maxim Integrated Products
1
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Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit MAX1845
ABSOLUTE MAXIMUM RATINGS (Note 1)
V+ to AGND..............................................................-0.3 to +30V VCC to AGND............................................................-0.3V to +6V VDD to PGND............................................................-0.3V to +6V AGND to PGND .....................................................-0.3V to +0.3V PGOOD, OUT_ to AGND..........................................-0.3V to +6V OVP, UVP, ILIM_, FB_, REF, SKIP, TON, ON_ to AGND......................-0.3V to (VCC + 0.3V) DL_ to PGND ..............................................-0.3V to (VDD + 0.3V) BST_ to AGND........................................................-0.3V to +36V CS_ to AGND.............................................................-6V to +30V DH1 to LX1 ..............................................-0.3V to (VBST1 + 0.3V) LX_ to BST_ ..............................................................-6V to +0.3V DH2 to LX2 ..............................................-0.3V to (VBST2 + 0.3V) REF Short Circuit to GND ...........................................Continuous Continuous Power Dissipation (TA = +70C) 28-Pin QSOP (derate 10.8mW/C above +70C)........860mW 36-Pin 6mm 6mm Thin QFN (derate 26.3mW/C above +70C) .............................2105mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Note 1: For the MAX1845EEI, AGND and PGND refer to a single pin designated GND.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VDD = VCC = 5V, SKIP = AGND, V+ = 15V, TA = 0C to +85C, typical values are at +25C, unless otherwise noted.)
PARAMETER PWM CONTROLLERS Input Voltage Range V+ VCC/VDD Battery voltage, V+ VCC, VDD V+ = 2V to 28V, ILOAD = 0 to 8A, SKIP = VCC, +25C to +85C VOUT1 V+ = 2V to 28V, ILOAD = 0 to 8A, SKIP = VCC, 0C to +85C V+ = 4.5V to 28V, ILOAD = 0 to 4A, SKIP = VCC, +25C to +85C VOUT2 V+ = 4.5V to 28V, ILOAD = 0 to 4A, SKIP = VCC, 0C to +85C OUT1, OUT2 OVP, FB_ OVP, ILIM_ FB1 OUT_ Input Resistance FB_ Input Bias Current Soft-Start Ramp Time ROUT1 ROUT2 IFB Zero to full ILIM VOUT1 = 1.5V VOUT2 = 2.5V FB1 to AGND FB1 to VCC FB1 to OUT1 FB1 to AGND FB1 to VCC FB1 to OUT1 FB2 to AGND FB2 to OUT2 FB2 to AGND FB2 to OUT2 2 4.5 1.782 1.485 0.99 1.773 1.477 0.985 2.475 0.99 2.463 0.985 1 0.05 VCC 1.5 1.9 75 100 -0.1 1700 0.1 2.0 0.1 1.8 1.5 1 1.8 1.5 1 2.5 1 2.5 1 28 5.5 1.818 1.515 1.01 1.827 1.523 1.015 2.525 1.01 V 2.537 1.015 5.5 0.15 VCC 0.4 2.1 k A s V V V V V SYMBOL CONDITIONS MIN TYP MAX UNITS
DC Output Voltage OUT1 (Note 2)
DC Output Voltage OUT2 (Note 2)
Output Voltage Adjust Range Dual-Mode Threshold, Low Dual-Mode Threshold, High
2
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Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDD = VCC = 5V, SKIP = AGND, V+ = 15V, TA = 0C to +85C, typical values are at +25C, unless otherwise noted.)
PARAMETER SYMBOL V+ = 24V, VOUT1 = 2V CONDITIONS TON = AGND On-Time, Side 1 (Note 3) tON1 TON = REF TON = float TON = VCC TON = AGND On-Time, Side 2 (Note 3) tON2 V+ = 24V, VOUT2 = 2V TON = REF TON = float TON = VCC TON = AGND On-Time Tracking (Note 3) On-time 2 with respect to ontime 1 tOFF ICC IDD I+ FB_ forced above the regulation point FB_ forced above the regulation point Measured at V+ ON1 = ON2 = AGND, OVP = VCC or AGND ON1 = ON2 = AGND, VOVP = 1.8V ON1 = ON2 = AGND ON1 = ON2 = AGND, measured at V+, VCC = AGND or 5V VREF VCC = 4.5V to 5.5V, no external REF load IREF = 0 to 50A REF in regulation Falling edge, hysteresis = 40mV OVP = AGND, with respect to errorcomparator trip threshold 1V < VOVP < 1.8V, external feedback, measured at FB_ with respect to VOVP Overvoltage Comparator Offset (Adjustable-Threshold Mode) 1V < VOVP < 1.8V, internal feedback, measured at OUT_ with respect to OUT_ regulation point 1V < VOVP < 1.8V FB_ forced 2% above trip threshold UVP = VCC, with respect to error-comparator trip threshold From ON_ signal going high 65 10 112 -28 10 1.6 114 0 117 28 1.98 TON = REF TON = float TON = VCC Minimum Off-Time (Note 3) Quiescent Supply Current (VCC) Quiescent Supply Current (VDD) Quiescent Supply Current (V+) Shutdown Supply Current (VCC) Shutdown Supply Current (VDD) Shutdown Supply Current (V+) Reference Voltage Reference Load Regulation REF Sink Current REF Fault Lockout Voltage Overvoltage Trip Threshold (Fixed-Threshold Mode) MIN 120 153 222 316 160 205 301 432 125 125 125 125 TYP 137 174 247 353 182 234 336 483 135 135 135 135 400 1100 <1 25 <1 1 <1 <1 2 MAX 153 195 272 390 204 263 371 534 145 145 145 145 500 1500 5 70 5 5 5 5 2.02 0.01 ns A A A A A A V V A V % mV % ns ns UNITS
MAX1845
-3.5 -100
0 <1 1.5 70
+3.5 100
% nA s
OVP Input Leakage Current Overvoltage Fault Propagation Delay Output Undervoltage Threshold Output Undervoltage Protection Blanking Time
75 30
% ms
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Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit MAX1845
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDD = VCC = 5V, SKIP = AGND, V+ = 15V, TA = 0C to +85C, typical values are at +25C, unless otherwise noted.)
PARAMETER Current-Limit Threshold (Fixed) Current-Limit Threshold (Adjustable) ILIM_ Adjustment Range Negative Current-Limit Threshold (Fixed) Thermal Shutdown Threshold VCC Undervoltage Lockout Threshold DH Gate-Driver On-Resistance (Note 4) DL Gate-Driver On-Resistance (Note 4) DL Gate-Driver On-Resistance (Note 4) DH_ Gate Driver Source/Sink Current DL_ Gate Driver Sink Current DL_ Gate Driver Source Current Logic Input High Voltage VIH VILIM_ VCS_ - AGND, ILIM_ = VCC, TA = +25 oC Hysteresis = 15oC Rising edge, hysteresis = 20mV, PWMs disabled below this level BST - LX forced to 5V DL, high state DL, low state MAX1845EEI MAX1845ETX MAX1845EEI MAX1845ETX MAX1845EEI MAX1845ETX 4.05 1.5 1.5 1.5 1.5 0.5 0.5 1 3 1 2.4 VCC 0.4 0.8 0.05 VCC 0.4 3.15 1.65 -3 -1 -12.5 +7.5 -10 +10 1.5 0.4 1 3.85 2.35 0.5 3 1 -7.5 +12.5 A A % % s V A V V SYMBOL CONDITIONS AGND - VCS_, ILIM_ = VCC AGND - VCS_, ILIM_ = 0.5V AGND - VCS_, ILIM_ = 1V MIN 40 40 85 0.3 -75 -60 160 4.4 5 6 5 6 1.7 2.7 TYP 50 50 100 MAX 60 60 115 2.5 -45 UNITS mV mV V mV
o
C
V A A A
VDH_ = 2.5V, VBST_ = VLX_ = 5V VDL_ = 2.5V VDL_ = 2.5V ON_, SKIP UVP ON_, SKIP UVP VCC level
Logic Input Low Voltage
VIL
V
TON Input Logic level
Float level REF level AGND level
Logic Input Current Logic Input Current PGOOD Trip Threshold (Lower) PGOOD Trip Threshold (Upper) PGOOD Propagation Delay PGOOD Output Low Voltage PGOOD Leakage Current
TON (AGND or VCC) ON_, SKIP, UVP With respect to error-comparator trip threshold, falling edge With respect to error-comparator trip threshold, rising edge Falling edge, FB_ forced 2% below PGOOD trip threshold ISINK = 1mA High state, forced to 5.5V
4
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Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VDD = VCC = 5V, SKIP = AGND, V+ = 15V, TA = -40C to +85C, unless otherwise noted.) (Note 5)
PARAMETER PWM CONTROLLERS Input Voltage Range V+ VCC/VDD VOUT1 Battery voltage, V+ VCC, VDD V+ = 2V to 28V, SKIP = VCC, ILOAD = 0 to 10A V+ = 2V to 28V, SKIP = VCC, ILOAD = 0 to 10A OUT1, OUT2 OVP, FB_ OVP, ILIM_ FB_ OUT_ Input Resistance FB_ Input Bias Current ROUT1 ROUT2 IFB TON = AGND On-Time, Side 1 (Note 3) tON1 V+ = 24V, VOUT1 = 2V TON = REF TON = float TON = VCC TON = AGND On-Time, Side 2 (Note 3) tON2 V+ = 24V, VOUT2 = 2V TON = REF TON = float TON = VCC TON = AGND On-Time Tracking (Note 3) On-time 2, with respect to on-time 1 tOFF ICC IDD I+ VREF FB forced above the regulation point FB forced above the regulation point Measured at V+ VCC = 4.5V to 5.5V, no external REF load IREF = 0 to 50uA OVP = GND, with respect to FB_ regulation point, no load UVP = VCC, with respect to FB_ regulation point, no load AGND - VCS_, ILIM_ = VCC 112 65 35 1.98 TON = REF TON = float TON = VCC Minimum Off-Time (Note 3) Quiescent Supply Current (VCC) Quiescent Supply Current (VDD) Quiescent Supply Current (V+) Reference Voltage Reference Load Regulation Overvoltage Trip Threshold (Fixed-Threshold Mode) Output Undervoltage Threshold Current-Limit Threshold (Fixed) VOUT1 = 1.5V VOUT2 = 2.5V FB1 to AGND FB1 to VCC FB1 to OUT1 FB2 to AGND FB2 to OUT2 2 4.5 1.773 1.477 0.985 2.463 0.985 1 0.05 VCC 1.5 1.9 75 100 -0.1 120 153 217 308 160 205 295 422 125 125 125 125 0.1 153 195 272 390 204 263 371 534 145 145 145 145 500 1500 5 70 2.02 0.01 117 75 65 ns A A A V V % % mV % ns ns 28 5.5 1.827 1.523 1.015 2.537 1.015 5.5 0.15 VCC 0.4 2.1 k A V V V V V V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1845
DC Output Voltage, OUT1 (Note 2)
DC Output Voltage, OUT2 (Note 2) Output Voltage Adjust Range Dual-Mode Threshold (Low) Dual-Mode Threshold (High)
VOUT2
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Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit MAX1845
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDD = VCC = 5V, SKIP = AGND, V+ = 15V, TA = -40C to +85C, unless otherwise noted.) (Note 5)
PARAMETER Current-Limit Threshold (Adjustable) VCC Undervoltage Lockout Threshold Logic Input High Voltage VIH SYMBOL CONDITIONS AGND - VCS_, ILIM_ = 0.5V AGND - VCS_, ILIM_ = 1V Rising edge, hysteresis = 20mV, PWMs disabled below this level ON_, SKIP UVP ON_, SKIP UVP TON (AGND or VCC) ON_, SKIP, UVP -3 -1 MIN 35 80 4.05 2.4 VCC 0.4 0.8 0.05 3 1 V TYP MAX 65 120 4.4 UNITS mV V
Logic Input Low Voltage Logic Input Current
VIL
V A
Note 2: When the inductor is in continuous conduction, the output voltage will have a DC regulation level higher than the error comparator threshold by 50% of the output voltage ripple. In discontinuous conduction (SKIP = AGND, light load), the output voltage will have a DC regulation higher than the error-comparator threshold by approximately 1.5% due to slope compensation. Note 3: On-time and off-time specifications are measured from 50% point to 50% point at DH_ with LX_ = GND, BST_ = 5V, and a 250pF capacitor connected from DH_ to LX_. Actual in-circuit times may differ due to MOSFET switching speeds. Note 4: Production testing limitations due to package handling require relaxed maximum on-resistance specifications for the QFN package. The MAX1845EEI and MAX1845ETX contain the same die, and the QFN package imposes no additional resistance in-circuit. Note 5: Specifications to -40C are guaranteed by design, not production tested.
__________________________________________Typical Operating Characteristics
(Circuit of Figure 1, components from Table 1, VIN = 15V, SKIP = GND, TON = unconnected, TA = +25C, unless otherwise noted.)
FREQUENCY vs. INPUT VOLTAGE (TON = FLOAT, SKIP = VCC)
MAX1845 toc01
FREQUENCY vs. LOAD CURRENT
400 350 300 FREQUENCY (kHz) 250 200 150 100 50 0 0.01 0.1 1 10 LOAD CURRENT (A) OUT2, SKIP = GND OUT2, SKIP = VCC OUT1, SKIP = GND FREQUENCY (kHz) OUT1, SKIP = VCC 400 350 300 250 200 150 100 50 0 4
OUT1
OUT2
IOUT1 = 8A IOUT2 = 4A 8 12 16 20 21
INPUT VOLTAGE (V)
6
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MAX1845 toc02
Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit MAX1845
Typical Operating Characteristics (continued)
(Circuit of Figure 1, components from Table 1, VIN = 15V, SKIP = GND, TON = unconnected, TA = +25C, unless otherwise noted.)
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (SKIP = VCC)
MAX1845 toc03A
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (SKIP = GND)
1000 900 SUPPLY CURRENT (A) 800 700 600 500 400 300 200 100 0 IDD (600nA typ) I+ ICC EFFICIENCY (%) VCC = VDD = 5V
MAX1845 toc03B
EFFICIENCY vs. LOAD CURRENT (8A COMPONENTS, SKIP = VCC)
90 80 70 60 50 40 30 20 10 OUT1 = 1.8V 0.01 0.1 1 10 V+ = 12V V+ = 7V V+ = 20V
MAX1845 toc04a
15.0 13.5 12.0 SUPPLY CURRENT (mA) 10.5 9.0 7.5 6.0 4.5 3.0 1.5 0 5 10 15 20 25 ICC I+ (25A TYP) VCC = VDD = 5V IDD
1100
100
30
5
10
15
20
25
30
SUPPLY VOLTAGE V+ (V)
SUPPLY VOLTAGE V+ (V)
LOAD CURRENT (A)
EFFICIENCY vs. LOAD CURRENT (8A COMPONENTS, SKIP = GND)
MAX1845 toc04b
EFFICIENCY vs. LOAD CURRENT (4A COMPONENTS, SKIP = VCC)
90 80 EFFICIENCY (%) 70 60 50 40 30 V+ = 12V V+ = 7V V+ = 20V
MAX1845 toc04c
EFFICIENCY vs. LOAD CURRENT (4A COMPONENTS, SKIP = GND)
MAX1845 toc04d
100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 0.01 0.1 1 OUT1 = 1.8V V+ = 20V V+ = 12V V+ = 7V
100
100
95 EFFICIENCY (%)
V+ = 7V
90 V+ = 20V 85 V+ = 12V 80
20 10 10 0.01 0.1
OUT2 = 2.5V 75 1 10 0.01 0.1
OUT2 = 2.5V 1 10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
CURRENT-LIMIT TRIP POINT vs. ILIM VOLTAGE
250 230 210 190 170 150 130 110 90 70 50 30 10 0 0.5 1.0 1.5 2.0 ILIM VOLTAGE (V)
MAX1845 toc05
NORMALIZED OVERVOLTAGE PROTECTION THRESHOLD vs. OVP VOLTAGE
1.9 NORMALIZED THRESHOLD (V) 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 2.5 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
MAX1845 toc06
2.0
LOAD-TRANSIENT RESPONSE (4A COMPONENTS, PWM MODE, VOUT2 = 2.5V)
MAX1845 toc07a
CURRENT-LIMIT TRIP POINT (mV)
VOUT2 100mV/div
IOUT2 2A/div
20s/div
OVP VOLTAGE (V)
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Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit MAX1845
Typical Operating Characteristics (continued)
(Circuit of Figure 1, components from Table 1, VIN = 15V, SKIP = GND, TON = unconnected, TA = +25C, unless otherwise noted.)
LOAD-TRANSIENT RESPONSE (8A COMPONENTS, PWM MODE, VOUT1 = 1.8V)
MAX1845 toc07b
STARTUP WAVEFORM (4A COMPONENTS, SKIP = GND, VOUT2 = 2.5V)
MAX1845 toc09
SHUTDOWN WAVEFORM (4A COMPONENTS, SKIP = GND, VOUT2 = 2.5V)
MAX1845 toc09
VOUT2 1V/div VOUT1 100mV/div
VOUT2 1V/div
IOUT2 2A/div IOUT1 5A/div
IOUT2 5A/div
20s/div
400s/div
100s/div
Pin Description
PIN NAME QSOP QFN Output Voltage Connection for the OUT1 PWM. Connect directly to the junction of the external inductor and output filter capacitors. OUT1 senses the output voltage to determine the on-time and also serves as the feedback input in fixed-output modes. Feedback Input for OUT1. Connect to GND for 1.8V fixed output or to VCC for 1.5V fixed output, or connect to a resistor-divider network from OUT1 for an adjustable output between 1V and 5.5V. Current-Limit Threshold Adjustment for OUT1. The current-limit threshold at CS1 is 0.1 times the voltage at ILIM1. Connect a resistor-divider network from REF to set the current-limit threshold between 25mV and 250mV (with 0.25V to 2.5V at ILIM). Connect to VCC to assert 50mV default current-limit threshold. Battery Voltage-Sense Connection. Connect to input power source. V+ is only used to adjust the DH_ on-time for pseudofixed-frequency operation. On-Time Selection Control Input. This four-level input pin sets the DH_ on-time to determine the operating frequency. TON 5 1 TON AGND REF Open VCC 6 2 SKIP FREQUENCY (OUT1) (kHz) 620 485 345 235 FREQUENCY (OUT2) (kHz) 460 355 255 170 FUNCTION
1
32
OUT1
2
33
FB1
3
34
ILIM1
4
35
V+
Pulse-Skipping Control Input. Connect to VCC for low-noise forced-PWM mode. Connect to AGND to enable pulse-skipping operation.
8
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Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit
Pin Description (continued)
PIN NAME QSOP 7 QFN 3 PGOOD Power-Good Open-Drain Output. PGOOD is low when either output voltage is off or is more than 10% above or below the normal regulation point. Overvoltage Protection Threshold. An overvoltage fault occurs if the voltage on FB1 or FB2 is greater than the programmed overvoltage trip threshold. Adjustment range is 1V (100%) to 1.8V (180%). Connect OVP to GND to set the default overvoltage threshold of 114% of nominal. Connect to VCC to disable OVP and clear the OVP latch. Undervoltage Protection Threshold. An undervoltage fault occurs if the voltage on FB1 or FB2 is less than the undervoltage trip threshold (70% of nominal). Connect UVP to VCC to enable undervoltage protection. Connect to GND to disable undervoltage protection and clear the UVP latch. +2.0V Reference Voltage Output. Bypass to GND with 0.22F (min) capacitor. Can supply 50A for external loads. OUT1 ON/OFF Control Input. Connect to AGND to turn OUT1 off. Connect to VCC to turn OUT1 on. OUT2 ON/OFF Control Input. Connect to AGND to turn OUT2 off. Connect to VCC to turn OUT2 on. Current-Limit Threshold Adjustment for OUT2. The current-limit threshold at CS2 is 0.1 times the voltage at ILIM2. Connect a resistor-divider network from REF to set the current-limit threshold between 25mV and 250mV (with 0.25V to 2.5V at ILIM). Connect to VCC to assert 50mV default current-limit threshold. Feedback Input for OUT2. Connect to GND for 2.5V fixed output, or connect to a resistor-divider network from OUT2 for an adjustable output between 1V and 5.5V. Output Voltage Connection for the OUT2 PWM. Connect directly to the junction of the external inductor and output filter capacitors. OUT2 senses the output voltage to determine the on-time and also serves as the feedback input in fixed-output modes. Current-Sense Input for OUT2. CS2 is the input to the current-limiting circuitry for valley current limiting. For lowest cost and highest efficiency, connect to LX2. For highest accuracy, use a sense resistor. See the Current-Limit Circuit (ILIM_) section. External Inductor Connection for OUT2. Connect to the switched side of the inductor. LX2 serves as the internal lower supply voltage rail for the DH2 high-side gate driver. High-Side Gate Driver Output for OUT2. Swings from LX2 to BST2. Boost Flying Capacitor Connection for OUT2. Connect to an external capacitor and diode according to the standard application circuit in Figure 1. See MOSFET Gate Drivers (DH_, DL_) section. Low-Side Gate-Driver Output for OUT2. DL2 swings from PGND to VDD. Supply Input for the DL Gate Drivers. Connect to system supply voltage, +4.5V to +5.5V. Bypass to PGND with a low-ESR 4.7F capacitor. Analog Supply Input. Connect to system supply voltage, +4.5V to +5.5V, with a 20 series resistor. Bypass to AGND with a 1F capacitor. Ground. Combined analog and power ground. Serves as negative input for CS_ amplifiers. FUNCTION
MAX1845
8
4
OVP
9
5
UVP
10 11 12
7 8 11
REF ON1 ON2
13
12
ILIM2
14
13
FB2
15
14
OUT2
16
15
CS2
17 18
16 18
LX2 DH2
19 20 21 22 23
19 20 21 22 --
BST2 DL2 VDD VCC GND
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9
Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit MAX1845
Pin Description (continued)
PIN NAME QSOP -- -- 24 QFN 23 24 26 AGND PGND DL1 Analog Ground. Serves as negative input for CS_ amplifiers. Connect backside pad to AGND. Power Ground Low-Side Gate-Driver Output for OUT1. DL1 swings from PGND to VDD. Boost Flying Capacitor Connection for OUT1. Connect to an external capacitor and diode according to the standard application circuit in Figure 1. See the MOSFET Gate Drivers (DH_, DL_) section. High-Side Gate Driver Output for OUT1. Swings from LX1 to BST1. External Inductor Connection for OUT1. Connect to the switched side of the inductor. LX1 serves as the internal lower supply voltage rail for the DH1 high-side gate driver. Current-Sense Input for OUT1. CS1 is the input to the current-limiting circuitry for valley current limiting. For lowest cost and highest efficiency, connect to LX1. For highest accuracy, use a sense resistor. See the Current-Limit Circuit (ILIM_) section. FUNCTION
25
27
BST1
26 27
28 30
DH1 LX1
28
31
CS1
--
6, 9, 10, 17, 25, 29, 36
N.C.
No Connection
Standard Application Circuit
The standard application circuit (Figure 1) generates a 1.8V and a 2.5V rail for general-purpose use in notebook computers. See Table 1 for component selections. Table 2 lists component manufacturers.
Detailed Description
The MAX1845 buck controller is designed for low-voltage power supplies for notebook computers. Maxim's proprietary Quick-PWM pulse-width modulator in the MAX1845 (Figure 2) is specifically designed for handling fast load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. The Quick-PWM architecture circumvents the poor load-transient timing problems of fixed-frequency current-mode PWMs while avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time and constant-off-time PWM schemes.
efficiency and eliminates the cost associated with the 5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, the 5V supply can be generated with an external linear regulator such as the MAX1615. The power input and 5V bias inputs can be connected together if the input source is a fixed 4.5V to 5.5V supply. If the 5V bias supply is powered up prior to the battery supply, the enable signal (ON1, ON2) must be delayed until the battery voltage is present to ensure startup. The 5V bias supply must provide V CC and gate-drive power, so the maximum current drawn is: IBIAS = ICC + f (QG1 + QG2) = 5mA to 30mA (typ) where ICC is 1mA typical, f is the switching frequency, and QG1 and QG2 are the MOSFET data sheet total gate-charge specification limits at VGS = 5V.
Free-Running, Constant-On-Time PWM Controller with Input Feed-Forward
The Quick-PWM control architecture is a pseudo-fixedfrequency, constant-on-time current-mode type with voltage feed-forward (Figure 3). This architecture relies on the output filter capacitor's effective series resistance (ESR) to act as a current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-
5V Bias Supply (VCC and VDD) The MAX1845 requires an external 5V bias supply in addition to the battery. Typically, this 5V bias supply is the notebook's 95% efficient 5V system supply. Keeping the bias supply external to the IC improves
10
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Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit MAX1845
time is determined solely by a one-shot whose pulse width is inversely proportional to input voltage and directly proportional to output voltage. Another one-shot sets a minimum off-time (400ns typ). The on-time oneshot is triggered if the error comparator is low, the lowside switch current is below the current-limit threshold, and the minimum off-time one-shot has timed out (Table 3). remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. The on-times for side 1 are set 35% higher than the ontimes for side 2. This is done to prevent audio-frequency "beating" between the two sides, which switch asynchronously for each side. The on-time is given by: On-Time = K (VOUT + 0.075V) / VIN where K is set by the TON pin-strap connection (Table 4), and 0.075V is an approximation to accommodate for the expected drop across the low-side MOSFET switch. One-shot timing error increases for the shorter on-time settings due to fixed propagation delays; it is approximately 12.5% at higher frequencies and 10% at lower frequencies. This translates to reduced switching-frequency accuracy at higher frequencies (Table 4). Switching frequency increases as a function of load current due to the increasing drop across the low-side MOSFET, which causes a faster inductor-current discharge ramp. The on-times guaranteed in the Electrical Characteristics tables are influenced by switching delays in the external high-side power MOSFET.
On-Time One-Shot (TON)
The heart of the PWM core is the one-shot that sets the high-side switch on-time for both controllers. This fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. The high-side switch on-time is inversely proportional to the battery voltage as measured by the V+ input, and proportional to the output voltage. This algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. The benefits of a constant switching frequency are twofold: First, the frequency can be selected to avoid noise-sensitive regions such as the 455kHz IF band; second, the inductor ripple-current operating point
VDD = 5V BIAS SUPPLY C9 4.7F C8 1F D3 CMPSH-3A VIN 7V TO 24V
R1 20
4 21 V 9 DD UVP 22 VCC 3 ILIM1 13 ILIM2 V+ ON1 11
C11 1F
12 ON2 8 OVP
ON/OFF CONTROLS C2 2 10F
MAX1845EEI
C1 3 10F OUTPUT1 1.8V, 8A C3 3 470F L1 2.2H D1 Q1 C5 0.1F Q2 25 26 27 24 BST1 DH1 LX1 DL1 BST2 DH2 LX2 DL2 CS2 19 18 17 20 16 C6 0.1F Q4 Q3
L2 4.7H
OUTPUT2 2.5V, 4A C4 470F
D2
R1 5m
C7 0.22F
5 TON 28 CS1 1 OUT1 10 REF 2 23 FB1 GND
OUT2 15 SKIP FB2 PGOOD 6 14 7 5V 100k R2 10m POWER-GOOD INDICATOR
Figure 1. Standard Application Circuit ______________________________________________________________________________________ 11
Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit MAX1845
Table 1. Component Selection for Standard Applications
COMPONENT Input Range SIDE 1: 1.8V AT 8A/ SIDE 2: 2.5V AT 4A 4.5V to 28V Fairchild Semiconductor FDS6612A or International Rectifier IRF7807 Fairchild Semiconductor FDS6670A or International Rectifier IRF7805 Fairchild Semiconductor FDS6982A Nihon EP10QY03 Central Semiconductor CMPSH-3A 2.2H Panasonic ETQP6F2R2SFA or Sumida CDRH127-2R4 4.7H Sumida CDRH124-4R7MC 10F, 25V Taiyo Yuden TMK432BJ106KM or TDK C4532X5R1E106M 470F, 6V Kemet T510X477M006AS or Sanyo 6TPB330M 5m, 1%, 1W IRC LR2512-01-R005-F or DALE WSL-2512-R005F 10m, 1%, 0.5W IRC LR2010-01-R010-F or DALE WSL-2010-R010F
Table 2. Component Suppliers
MANUFACTURER Central Semiconductor Dale/Vishay Fairchild Semiconductor International Rectifier IRC Kemet NIEC (Nihon) Sanyo Siliconix Sumida Taiyo Yuden TDK *Distributor FACTORY FAX [Country Code] 516-435-1110 [1] 516-435-1824 203-452-5664 [1] 203-452-5670 408-822-2181 [1] 408-721-1635 310-322-3331 [1] 310-322-3332 800-752-8708 [1] 828-264-7204 408-986-0424 [1] 408-986-1442 805-867-2555* [81] 3-3494-7414 619-661-6835 [81] 7-2070-1174 USA PHONE 408-988-8000 800-554-5565 847-956-0666 408-573-4150 847-390-4461 [1] 408-970-3950 [81] 3-3607-5144 [1] 408-573-4159 [1] 847-390-4405
Q1 High-Side MOSFET
Q2 Low-Side MOSFET
Q3, Q4 High/Low-Side MOSFETs D1, D2 Rectifier D3 Rectifier
L1 Inductor
both dead times. It occurs only in PWM mode (SKIP = high) when the inductor current reverses at light or negative load currents. With reversed inductor current, the inductor's EMF causes LX to go high earlier than normal, extending the on-time by a period equal to the low-to-high dead time. For loads above the critical conduction point, the actual switching frequency is: f= VOUT + VDROP1 t ON (VIN + VDROP2 )
L2 Inductor
C1 (3), C2 (2) Input Capacitor
C3 (3), C4 Output Capacitor
where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PC board resistances; VDROP2 is the sum of the resistances in the charging path; and tON is the on-time calculated by the MAX1845.
Automatic Pulse-Skipping Switchover
In skip mode (SKIP = GND), an inherent automatic switchover to PFM takes place at light loads. This switchover is effected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). For a 7V to 24V battery range, of this threshold is relatively constant, with only a minor dependence on battery voltage: K x VOUT_ VIN - VOUT_ I LOAD(SKIP) 2L VIN
RSENSE1
RSENSE2
Two external factors that influence switching-frequency accuracy are resistive drops in the two conduction loops (including inductor and PC board resistance) and the dead-time effect. These effects are the largest contributors to the change of frequency with changing load current. The dead-time effect increases the effective on-time, reducing the switching frequency as one or
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Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit MAX1845
V+ 2V TO 28V
ILIM1 VDD 5V INPUT VDD PGND* VDD V+ BST1 VCC - 1V 0.5V
V+
ILIM2
VCC - 1V 0.5V
VDD V+ BST2
DH1 LX1
MAX1845
DH2 LX2
CS1 VDD DL1
PWM CONTROLLER (FIGURE 3)
PWM CONTROLLER (FIGURE 3) VDD
CS2
DL2
OUT1 FB1 UVP OVP TON SKIP PGOOD
OUT 2 FB2 VCC 20 2V REF REF VDD
AGND* FAULT1 ON1 ON2 FAULT2 * IN THE MAX1845EEI, AGND AND PGND ARE INTERNALLY CONNECTED AND CALLED GND.
Figure 2. Functional Diagram
where K is the on-time scale factor (Table 4). The loadcurrent level at which PFM/PWM crossover occurs, ILOAD(SKIP), is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (Figure 4). For example, in the standard application circuit with VOUT1 = 2.5V, VIN = 15V, and K = 2.96s (Table 4), switchover to pulse-skipping operation occurs at ILOAD = 0.7A or about 1/6 full load. The crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used.
The switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values
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Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit MAX1845
V+ TOFF 1-SHOT TRIG
TON
ON-TIME COMPUTE TON TRIG 1-SHOT FROM ILIM COMPARATOR Q
FROM OUT
Q
S R ERROR AMP REF FROM ZERO-CROSSING COMPARATOR
Q
TO DH DRIVER
TO DL DRIVER S Q R SHUTDOWN
FROM OPPOSITE PWM OVP 1.14V
0.1V OUT_ TO OPPOSITE PWM R VCC - 1V S Q x2 FEEDBACK MUX (SEE FIGURE 9)
FB_
0.7V
1.1V R Q UVP FAULT TO PGOOD OR-GATE S TIMER
0.9V
Figure 3. PWM Controller (One Side Only)
include larger physical size and degraded load-transient response (especially at low input voltage levels). DC output accuracy specifications refer to the threshold of the error comparator. When the inductor is in continuous conduction, the output voltage will have a DC regulation higher than the trip level by 50% of the ripple. In discontinuous conduction (SKIP = GND, light-load), the output voltage will have a DC regulation higher than the trip level by approximately 1.5% due to slope compensation.
Forced-PWM Mode (SKIP = High)
The low-noise, forced-PWM mode (SKIP = high) disables the zero-crossing comparator, which controls the
14
low-side switch on-time. This causes the low-side gatedrive waveform to become the complement of the highside gate-drive waveform. This in turn causes the inductor current to reverse at light loads as the PWM loop strives to maintain a duty ratio of VOUT/VIN. The benefit of forced-PWM mode is to keep the switching frequency fairly constant, but it comes at a cost: The no-load battery current can be 10mA to 40mA, depending on the external MOSFETs. Forced-PWM mode is most useful for reducing audiofrequency noise, improving load-transient response, providing sink-current capability for dynamic output voltage adjustment, and improving the cross-regulation
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Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit MAX1845
Table 3. Operating Mode Truth Table
ON1 GND ON2 GND SKIP X DL1/DL2 High*/High* MODE Shutdown Run (PWM), Low Noise, Side 1 Only Run (PWM), Low Noise, Side 2 Only Run (PWM), Low Noise, Both Sides Active Run (PWM/PFM), Skip Mode, Side 1 Only Run (PWM/PFM), Skip Mode, Side 2 Only Run (PWM/PFM), Skip Mode, Both Sides Active Fault latch has been set by overvoltage protection circuit, undervoltage protection circuit, or thermal shutdown. Device will remain in fault mode until VCC power is cycled or ON1/ON2 is toggled. Normal operation with automatic PWM/PFM switchover for pulse skipping at light loads. Best light-load efficiency. Low-noise, fixed frequency PWM at all load conditions. Low noise, high IQ. COMMENTS Low-power shutdown state. If overvoltage protection is enabled, DL1 and DL2 are forced to VDD, ensuring overvoltage protection, ICC < 1A (typ).
VCC GND VCC VCC GND VCC
GND VCC VCC GND VCC VCC
VCC VCC VCC GND GND GND
Switching/High* High*/Switching Switching/ Switching Switching/High* High*/Switching Switching/ Switching
VCC
VCC
X
High*/High*
Fault
*DL_ high only if overvoltage protection enabled (see Output Overvoltage Protection section).
of multiple-output applications that use a flyback transformer or coupled inductor.
Current-Limit Circuit (ILIM_)
The current-limit circuit employs a unique "valley" currentsensing algorithm. If the magnitude of the current-sense signal at CS_ is above the current-limit threshold, the PWM is not allowed to initiate a new cycle (Figure 5). The actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the sense resistance, inductor value, and battery voltage. There is also a negative current limit that prevents excessive reverse inductor currents when VOUT is sinking current. The negative current-limit threshold is set to approximately 120% of the positive current limit and therefore tracks the positive current limit when ILIM is adjusted. The current-limit threshold is adjusted with an internal 5A current source and an external resistor at ILIM. The current-limit threshold adjustment range is from 25mV to 250mV. In the adjustable mode, the current-limit threshold voltage is precisely 1/10 the voltage seen at ILIM. The threshold defaults to 50mV when ILIM is con-
nected to VCC. The logic threshold for switchover to the 50mV default value is approximately VCC - 1V. Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the current-sense signal seen by CS_ and GND. Mount or place the IC close to the low-side MOSFET and sense resistor with short, direct traces, making a Kelvin sense connection to the sense resistor. In Figure 1, the Schottky diodes (D1 and D2) provide current paths parallel to the Q2/R SENSE and Q4/R SENSE current paths, respectively. Accurate current sensing requires D1/D2 to be off while Q2/Q4 conducts. Avoid large current-sense voltages that, combined with the voltage across Q2/Q4, would allow D1/D2 to conduct. If very large sense voltages are used, connect D1/D2 in parallel with Q2/Q4 only.
MOSFET Gate Drivers (DH_, DL_)
The DH and DL drivers are optimized for driving moderate-size, high-side and larger, low-side power MOSFETs. This is consistent with the low duty factor seen in the notebook CPU environment, where a large VBATT - VOUT differential exists. An adaptive dead-time circuit monitors the DL output and prevents the highside FET from turning on until DL is fully off. There must
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Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit MAX1845
i VBATT -VOUT = t L INDUCTOR CURRENT IPEAK IPEAK ILOAD INDUCTOR CURRENT
ILOAD = IPEAK/2
ILIMIT
0 ON-TIME
TIME
0
TIME
Figure 4. Pulse-Skipping/Discontinuous Crossover Point
Figure 5. ``Valley'' Current-Limit Threshold Point
be a low-resistance, low-inductance path from the DL driver to the MOSFET gate for the adaptive dead-time circuit to work properly. Otherwise, the sense circuitry in the MAX1845 will interpret the MOSFET gate as "off" while there is actually still charge left on the gate. Use very short, wide traces measuring 10 to 20 squares (50 to 100 mils wide if the MOSFET is 1 inch from the MAX1845). The dead time at the other edge (DH turning off) is determined by a fixed 35ns (typ) internal delay. The internal pulldown transistor that drives DL low is robust, with a 0.5 typical on-resistance. This helps prevent DL from being pulled up during the fast risetime of the inductor node, due to capacitive coupling from the drain to the gate of the low-side synchronousrectifier MOSFET. However, for high-current applications, some combinations of high- and low-side FETs might be encountered that will cause excessive gatedrain coupling, which can lead to efficiency-killing, EMI-producing shoot-through currents. This is often remedied by adding a resistor in series with BST, which increases the turn-on time of the high-side FET without degrading the turn-off time (Figure 6).
A continuously adjustable analog soft-start function can be realized by adding a capacitor in parallel with the ILIM external resistor-divider network. This soft-start method requires a minimum interval between powerdown and power-up to discharge the capacitor.
Power-Good Output (PGOOD)
The PGOOD window comparator continuously monitors the output voltage for both overvoltage and undervoltage conditions. In shutdown, standby, and soft-start, PGOOD is actively held low. After a digital soft-start has terminated, PGOOD is released when the output is within 10% of the error-comparator threshold. The PGOOD output is a true open-drain type with no parasitic ESD diodes. Note that the PGOOD window detector is independent of the output overvoltage and undervoltage protection (UVP) thresholds.
Output Overvoltage Protection
The output voltage can be continuously monitored for overvoltage. When overvoltage protection is enabled, if the output exceeds the overvoltage threshold, overvoltage protection is triggered and the DL low-side gatedrivers are forced high. This activates the low-side MOSFET switch, which rapidly discharges the output capacitor and reduces the input voltage. Note that DL latching high causes the output voltage to dip slightly negative when energy has been previously stored in the LC tank circuit. For loads that cannot tolerate a negative voltage, place a power Schottky diode across the output to act as a reverse polarity clamp. Connect OVP to GND to enable the default trip level of 114% of the nominal output. To adjust the overvoltage protection trip level, apply a voltage from 1V (100%) to 1.8V (180%) at OVP. Disable the overvoltage protection by connecting OVP to VCC.
POR, UVLO, and Soft-Start
Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch and soft-start counter and preparing the PWM for operation. VCC undervoltage lockout (UVLO) circuitry inhibits switching. DL is low if the overvoltage protection (OVP) is disabled. DL is high if the overvoltage protection is enabled (see the Output Overvoltage Protection section) when VCC rises above 4.2V, whereupon an internal digital soft-start timer begins to ramp up the maximum allowed current limit. The ramp occurs in five steps: 20%, 40%, 60%, 80%, and 100%; 100% current is available after 1.7ms 50%.
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Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit MAX1845
+5V VIN
BST
5
DH
LX
MAX1845
Figure 6. Reducing the Switching-Node Rise Time
The overvoltage trip level depends on the internal or external output voltage feedback divider and is restricted by the output voltage adjustment range (1V to 5.5V) and by the absolute maximum rating of OUT_. Setting the overvoltage threshold higher than the output voltage adjustment range is not recommended.
1) Input Voltage Range. The maximum value (VIN(MAX)) must accommodate the worst-case high AC adapter voltage. The minimum value (VIN(MIN)) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. Lower input voltages result in better efficiency. 2) Maximum Load Current. There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. 3) Switching Frequency. This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage due to MOSFET switching losses that are proportional to frequency and VIN2. 4) Inductor Operating Point. This choice provides trade-offs between size vs. efficiency. Low inductor values cause large ripple currents, resulting in the smallest size, but poor efficiency and high output noise. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further sizereduction benefit. The MAX1845's pulse-skipping algorithm initiates skip mode at the critical conduction point. So, the inductor operating point also determines the loadcurrent value at which PFM/PWM switchover occurs. The optimum point is usually found between 20% and 50% ripple current.
Output Undervoltage Protection
The output voltage can be continuously monitored for undervoltage. When undervoltage protection is enabled (UVP = VCC), if the output is less than 70% of the error-amplifier trip voltage, undervoltage protection is triggered. If an overvoltage protection threshold is set, the DL low-side gate driver is forced high. This activates the low-side MOSFET switch, which rapidly discharges the output capacitor, reduces the input voltage, and grounds the outputs. If the overvoltage protection is disabled (OVP = VCC) and an undervoltage event occurs, the gate drivers are turned off and the outputs float. Connect UVP to GND to disable undervoltage protection. Note that DL latching high causes the output voltage to dip slightly negative when energy has been previously stored in the LC tank circuit. For loads that cannot tolerate a negative voltage, place a power Schottky diode across the output to act as a reverse polarity clamp. Also, note the nonstandard logic levels if actively driving UVP (see the Electrical Characteristics).
Inductor Selection
The switching frequency (on-time) and operating point (% ripple or LIR) determine the inductor value as follows: VOUT (VIN - VOUT ) L= VIN x f x LIR x I LOAD(MAX) Example: ILOAD(MAX) = 8A, VIN = 15V, VOUT = 1.8V, f = 300kHz, 25% ripple current or LIR = 0.25: 1.8V (15V - 1.8V) L= = 2.3H 15V x 345kHz x 0.25 x 8A
Design Procedure
Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design:
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Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit MAX1845
Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): IPEAK = ILOAD(MAX) + [(LIR / 2) ILOAD(MAX)] 7a). Use the worst-case value for RDS(ON) from the MOSFET data sheet, and add a margin of 0.5%/C for the rise in RDS(ON) with temperature. Use the calculated RDS(ON) and IL(MIN) from step 1 above to determine the current-limit threshold voltage. If the default 50mV threshold is unacceptable, set the threshold value as in step 2 above. In all cases, ensure an acceptable current limit considering current-sense and resistor accuracies.
Transient Response
The inductor ripple current also impacts transientresponse performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty factor, which can be calculated from the ontime and minimum off-time: VSAG = where: K (VOUT + 0.075V) VIN K (VOUT + 0.075V) VOUT + min off - time where minimum off-time = 400ns typ (Table 4). DUTY = The amount of overshoot during a full-load to no-load transient due to stored inductor energy can be calculated as: VSOAR = L IPEAK2 / (2 COUT VOUT) where IPEAK is the peak inductor current. (I LOAD(MAX) )2 x L 2 x CF x DUTY (VIN(MIN) - VOUT )
Output Capacitor Selection
The output filter capacitor must have low enough ESR to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. Also, the capacitance value must be high enough to absorb the inductor energy going from a full-load to noload condition without tripping the OVP circuit. For CPU core voltage converters and other applications where the output is subject to violent load transients, the output capacitor's size depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: VDIP RESR I LOAD(MAX) In non-CPU applications, the output capacitor's size depends on how much ESR is needed to maintain an acceptable level of output voltage ripple: RESR VP -P LIR x I LOAD(MAX)
Determining the Current Limit
For most applications, set the MAX1845 current limit by the following procedure: 1) Determine the minimum (valley) inductor current (IL(MIN)) under conditions when VIN is small, VOUT is large, and load current is maximum. The minimum inductor current is ILOAD minus half the ripple current (Figure 4). 2) The sense resistor determines the achievable current-limit accuracy. There is a trade-off between current-limit accuracy and sense-resistor power dissipation. Most applications employ a currentsense voltage of 50mV to 100mV. Choose a sense resistor such that: RSENSE = Current-Limit Threshold Voltage / IL(MIN) Extremely cost-sensitive applications that do not require high-accuracy current sensing can use the onresistance of the low-side MOSFET switch in place of the sense resistor by connecting CS_ to LX_ (Figure
18
MAX1845
LX
MAX1845
LX
DL
DL
CS
CS
a)
b)
Figure 7. Current-Sense Configurations
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Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit MAX1845
Table 4. Frequency Selection Guidelines
TON SETTING VCC FLOAT REF AGND SIDE 1 FREQUENCY (kHz) 235 345 485 620 SIDE 1 K-FACTOR (s) 4.24 2.96 2.08 1.63 SIDE 2 FREQUENCY (kHz) 170 255 355 460 SIDE 2 K-FACTOR (s) 5.81 4.03 2.81 2.18 APPROXIMATE K-FACTOR ERROR (%) 10 10 12.5 12.5
The actual microfarad capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of tantalums, OS-CONsTM, and other electrolytics). When using low-capacity filter capacitors such as ceramic or polymer types, capacitor size is usually determined by the capacity needed to prevent VSAG and VSOAR from causing problems during load transients. Also, the capacitance must be great enough to prevent the inductor's stored energy from launching the output above the overvoltage protection threshold. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section).
Output Capacitor Stability Considerations
Stability is determined by the value of the ESR zero relative to the switching frequency. The point of instability is given by the following equation: f f ESR SW where: f ESR = 1 2 x x RESR x CF
10m (max) ESR. Their typical combined ESR results in a zero at 11.3kHz, well within the bounds of stability. Do not put high-value ceramic capacitors directly across the outputs without taking precautions to ensure stability. Large ceramic capacitors can have a highESR zero frequency and cause erratic, unstable operation. However, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the inductor and connecting OUT_ or the FB_ divider close to the inductor. Unstable operation manifests itself in two related but distinctly different ways: double-pulsing and feedbackloop instability. Double-pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This "fools" the error comparator into triggering a new cycle immediately after the 400ns minimum off-time period has expired. Double-pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability, which is caused by insufficient ESR. Loop instability can result in oscillations at the output after line or load perturbations that can trip the overvoltage protection latch or cause the output voltage to fall below the tolerance limit. The easiest method for checking stability is to apply a very fast zero-to-max load transient (refer to the MAX1845 EV kit manual) and carefully observe the output voltage ripple envelope for overshoot and ringing. It helps to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under- or overshoot.
For a typical 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum and OS-CON capacitors in widespread use at the time of publication have typical ESR zero frequencies of 15kHz. In the design example used for inductor selection, the ESR needed to support 20mVP-P ripple is 20mV/2A = 10m. Three 470F/6V Kemet T510 low-ESR tantalum capacitors in parallel provide
OS-CON is a trademark of Sanyo.
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Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit MAX1845
Input Capacitor Selection
The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. Nontantalum chemistries (ceramic, aluminum, or OSCON) are preferred due to their resistance to power-up surge currents: V OUT VIN - VOUT I RMS = ILOAD VIN become an issue until the input is greater than approximately 15V. Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied, due to the squared term in the CV2f switching loss equation. If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when subjected to VIN(MAX), reconsider the choice of MOSFET. Calculating the power dissipation in Q1 due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turnoff times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for bench evaluation, preferably including a verification using a thermocouple mounted on Q1: PD(Q1 switching) = CRSS x VIN(MAX)2 x f x ILOAD IGATE
(
)
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability (>5A) when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention. For maximum efficiency, choose a high-side MOSFET (Q1) that has conduction losses equal to the switching losses at the optimum battery voltage (15V). Check to ensure that the conduction losses at the minimum input voltage do not exceed the package thermal limits or violate the overall thermal budget. Check to ensure that conduction losses plus switching losses at the maximum input voltage do not exceed the package ratings or violate the overall thermal budget. Choose a low-side MOSFET (Q2) that has the lowest possible RDS(ON), comes in a moderate to small package (i.e., SO-8), and is reasonably priced. Ensure that the MAX1845 DL gate driver can drive Q2; in other words, check that the gate is not pulled up by the highside switch turning on due to parasitic drain-to-gate capacitance, causing cross-conduction problems. Switching losses are not an issue for the low-side MOSFET since it is a zero-voltage switched device when used in the buck topology.
where CRSS is the reverse transfer capacitance of Q1, and IGATE is the peak gate-drive source/sink current (1A typ). For the low-side MOSFET, Q2, the worst-case power dissipation always occurs at maximum battery voltage: VOUT ILOAD2 x RDS(ON) PD(Q2) = 1 VIN(MAX ) The absolute worst case for MOSFET power dissipation occurs under heavy overloads that are greater than ILOAD(MAX) but are not quite high enough to exceed the current limit. To protect against this possibility, "overdesign" the circuit to tolerate: ILOAD = ILIMIT(HIGH) + (LIR / 2) ILOAD(MAX) where I LIMIT(HIGH) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. If short-circuit protection without overload protection is adequate, enable overvoltage protection, and use ILOAD(MAX) to calculate component stresses. Choose a Schottky diode (D1) having a forward voltage low enough to prevent the Q2 MOSFET body diode from turning on during the dead time. As a general rule, a diode having a DC current rating equal to 1/3 of the load current is sufficient. This diode is optional and can be removed if efficiency is not critical.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty cycle extremes. For the high-side MOSFET, the worst-casepower dissipation (PD) due to resistance occurs at minimum battery voltage: V PD(Q1 resistance) = OUT ILOAD2 x RDS(ON) VIN(MIN) Generally, a small high-side MOSFET is desired in order to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power-dissipation limits often limits how small the MOSFET can be. Again, the optimum occurs when the switching (AC) losses equal the conduction (RDS(ON)) losses. High-side switching losses do not usually
20
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Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit
Applications Information
Dropout Performance
The output voltage adjust range for continuous-conduction operation is restricted by the nonadjustable 500ns (max) minimum off-time one-shot. For best dropout performance, use the slower on-time settings. When working with low input voltages, the duty-cycle limit must be calculated using the worst-case values for on- and offtimes. Manufacturing tolerances and internal propagation delays introduce an error to the TON K-factor. This error is greater at higher frequencies (Table 4). Also, keep in mind that transient response performance of buck regulators operating close to dropout is poor, and bulk output capacitance must often be added (see the VSAG equation in the Design Procedure section). The absolute point of dropout is when the inductor current ramps down during the minimum off-time (IDOWN) as much as it ramps up during the on-time (IUP). The ratio h = IUP / IDOWN is an indicator of ability to slew the inductor current higher in response to increased load and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current will be less able to increase during each switching cycle, and VSAG will greatly increase unless additional output capacitance is used. A reasonable minimum value for h is 1.5, but this may be adjusted up or down to allow trade-offs between V SAG , output capacitance, and minimum operating voltage. For a given value of h, calculate the minimum operating voltage as follows: VIN(MIN) = [(VOUT + VDROP1) / {1 - (tOFF(MIN) h / K)}] + VDROP2 - VDROP1 where VDROP1 and VDROP2 are the parasitic voltage drops in the discharge and charge paths (see the OnTime One-Shot (TON) section), tOFF(MIN) is from the Electrical Characteristics, and K is taken from Table 4. The absolute minimum input voltage is calculated with h = 1. If the calculated VIN(MIN) is greater than the required minimum input voltage, then reduce the operating frequency or add output capacitance to obtain an acceptable VSAG. If operation near dropout is anticipated, calculate VSAG to ensure adequate transient response. Dropout Design Example: VOUT = 1.8V fsw = 600kHz K = 1.63s, worst-case K = 1.4175s tOFF(MIN) = 500ns VDROP1 = VDROP2 = 100mV h = 1.5 VIN(MIN) = (1.8V + 0.1V) / [1 - (0.5s 1.5) / 1.4175s] + 0.1V - 0.1V = 3.8V Calculating again with h = 1 gives an absolute limit of dropout: VIN(MIN) = (1.8V + 0.1V) / [1 - (0.5s 1) / 1.4175s] + 0.1V - 0.1V = 2.8V Therefore, VIN must be greater than 2.8V, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 3.8V.
MAX1845
Fixed Output Voltages
The MAX1845's dual-mode operation allows the selection of common voltages without requiring external components (Figure 8). Connect FB1 to GND for a fixed 1.8V output or to VCC for a 1.5V output, or connect FB1 directly to OUT1 for a fixed 1V output. Connect FB2 to GND for a fixed 2.5V output or to OUT2 for a fixed 1V output.
Setting VOUT_ with a Resistor-Divider The output voltage can be adjusted from 1V to 5.5V with a resistor-divider network (Figure 9). The equation for adjusting the output voltage is:
R1 VOUT_ = VFB_ 1 + R2 where VFB_ is 1.0V and R2 is about 10k.
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switching losses and clean, stable operation. This is especially true for dual converters, where one channel can affect the other. The switching power stages require particular attention (Figure 10). Refer to the MAX1845 evaluation kit data sheet for a specific layout example. Use a four-layer board. Use the top side for power components and the bottom side for the IC and the sensitive ground components. Use the two middle layers as ground planes, with interconnections between the top and bottom layers as needed. If possible,
21
______________________________________________________________________________________
Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit MAX1845
OUT1 FIXED 1.5V FIXED 1.8V TO ERROR AMP1 TO ERROR FIXED AMP2 2.5V MAX1845 DL_ CS_ FB1 0.1V FB2 OUT_ FB_ R2 R1 OUT2 DH_ VOUT VBATT
2V
MAX1845
0.1V
GND
Figure 8. Feedback Mux
Figure 9. Setting VOUT with a Resistor-Divider
mount all of the power components on the top side of the board, with connecting terminals flush against one another. Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. Short power traces and load connections are essential for high efficiency. Using thick copper PC boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. Place the current-sense resistors close to the top-side star-ground point (where the IC ground connects to the top-side ground plane) to minimize current-sensing errors. Avoid additional current-sensing errors by using a Kelvin connection from CS_ pins to the sense resistors. The following guidelines are in order of importance: * Keep the space between the ground connection of the current-sense resistors short and near the via to the IC ground pin. * Minimize the resistance on the low-side path. The low-side path starts at the ground of the low-side FET, goes through the low-side FET, through the inductor, through the output capacitor, and returns to the ground of the low-side FET. Minimize the resistance by keeping the components close together and the traces short and wide. * Minimize the resistance in the high-side path. This path starts at VIN, goes through the high-side FET,
22
USE AGND PLANE TO: - BYPASS VCC AND REF - TERMINATE EXTERNAL FB, ILIM, OVP DIVIDERS, IF USED - PIN-STRAP CONTROL INPUTS AGND PLANE
USE PGND PLANE TO: - BYPASS VDD - CONNECT IC GROUND TO TOP-SIDE STAR GROUND
PGND PLANE VIA TO TOP-SIDE GROUND
AGND PLANE
VIN Q1 Q3
Q2 CIN CIN CIN L1
D1 D2
Q4
L2
C1
C2
VIA TO OUT1
NOTCH VIA TO CS1
VIA TO PGND PLANE AND IC GND TOP-SIDE GROUND PLANE
Figure 10. PC Board Layout Example
______________________________________________________________________________________
Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit
through the inductor, through the input capacitor, and back to the input. * When trade-offs in trace lengths must be made, it's preferable to allow the inductor charging path to be made longer than the discharge path. For example, it's better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. * Route high-speed switching nodes (BST_, LX_, DH_, and DL_) away from sensitive analog areas (REF, ILIM_, FB_). 5) On the board's top side (power planes), make a star ground to minimize crosstalk between the two sides. The top-side star ground is a star connection of the input capacitors, side 1 low-side MOSFET, and side 2 low-side MOSFET. Keep the resistance low between the star ground and the source of the lowside MOSFETs for accurate current limit. Connect the top-side star ground (used for MOSFET, input, and output capacitors) to the small PGND island with a short, wide connection (preferably just a via). Minimize crosstalk between side 1 and side 2 by directing their switching ground currents into the star ground with a notch as shown in Figure 10. If multiple layers are available (highly recommended), create PGND1 and PGND2 islands on the layer just below the top-side layer (refer to the MAX1845 EV kit for an example) to act as an EMI shield. Connect each of these individually to the star-ground via, which connects the top side to the PGND plane. Add one more solid ground plane under the IC to act as an additional shield, and also connect that to the star-ground via. 6) Connect the output power planes directly to the output filter capacitor positive and negative terminals with multiple vias.
MAX1845
Layout Procedure
1) Place the power components first, with ground terminals adjacent (sense resistor, C IN -, C OUT -, D1 anode). If possible, make all these connections on the top layer with wide, copper-filled areas. 2) Mount the controller IC adjacent to the synchronous rectifiers MOSFETs, preferably on the back side in order to keep CS_, GND, and the DL_ gate-drive line short and wide. The DL_ gate trace must be short and wide, measuring 10 squares to 20 squares (50mils to 100mils wide if the MOSFET is 1 inch from the controller IC). 3) Group the gate-drive components (BST_ diode and capacitor, VDD bypass capacitor) together near the controller IC. 4) Make the DC-DC controller ground connections as follows: Create a small analog ground plane (AGND) near the IC. Connect this plane directly to GND under the IC, and use this plane for the ground connection for the REF and V CC bypass capacitors, FB_, OVP, and ILIM_ dividers (if any). Do not connect the AGND plane to any ground other than the GND pin. Create another small ground island (PGND), and use it for the VDD bypass capacitor, placed very close to the IC. Connect the PGND plane directly to GND from the outside of the IC.
Chip Information
TRANSISTOR COUNT: 4795 PROCESS: BiCMOS
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23
Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit MAX1845
Pin Configurations
V+ ILIM1
35 34
TOP VIEW
OUT1 1 FB1 2 ILIM1 3 V+ 4 TON 5 SKIP 6 PGOOD 7 OVP 8 UVP 9 REF 10 ON1 11 ON2 12 ILIM2 13 FB2 14 28 CS1 27 LX1 26 DH1 25 BST1 24 DL1 TON SKIP PGOOD OVP UVP N.C. REF ON1 N.C.
1 2 3 4 5 6 7 8 9
36
33
32
31
30
29
28
FB1 OUT1 CS1 LX1 N.C. DH1
N.C.
27 26 25 24 23 22 21 20 19 10 11 12 13 14 15 16 17 18
BST1 DL1 N.C. PGND AGND VCC VDD DL2 BST2
MAX1845EEI
MAX1845ETX
23 GND 22 VCC 21 VDD 20 DL2 19 BST2 18 DH2 17 LX2 16 CS2 15 OUT2
ON2 ILIM2 FB2 OUT2 CS2 LX2
N.C.
N.C.
THIN QFN
QSOP
24
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DH2
Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit MAX1845
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QSOP.EPS
Note: The MAX1845EEI does not have a heat slug.
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25
Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit MAX1845
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
D2 D D/2 k
C L
b D2/2
E/2 E2/2 E (NE-1) X e
C L
E2
k
e (ND-1) X e
L
C L
C L
L
L
e
e
A1
A2
A
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 36, 40L QFN THIN, 6x6x0.8 mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0141
1 2
B
26
______________________________________________________________________________________
QFN THIN 6x6x0.8.EPS
Dual, High-Efficiency, Step-Down Controller with Accurate Current Limit
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX1845
COMMON DIMENSIONS
PKG. CODES T3666-1 T4066-1
EXPOSED PAD VARIATIONS
D2 E2 MIN. NOM. MAX. MIN. NOM. MAX. 3.60 4.00 3.70 4.10 3.80 4.20 3.60 4.00 3.70 4.10 3.80 4.20
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
PROPRIETARY INFORMATION
9. DRAWING CONFORMS TO JEDEC MO220. 10. WARPAGE SHALL NOT EXCEED 0.10 mm.
TITLE:
PACKAGE OUTLINE 36, 40L QFN THIN, 6x6x0.8 mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0141
2 2
B
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
27 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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